Have you ever thought of getting your A2000 up and running again but were hesitating to place the old bulky Commodore 1084S monitor back onto your desk. This is the solution for you.
Principle of Operation
I wanted to connect my regular LCD monitor to the Amiga. Unfortunately the Amiga provides a PAL/NTSC resolution image at the Video output port, while the PC monitor requires at least a horizontal frequency of around 30 kHz.
The Amiga community solved this problem by introducing the scandoubler / flickerfixer: The video image is stored to some RAM and sent to a VGA connector at double scan rate.
Sounds simple and is especially simple on the A2000 as this model has an extra video slot for connecting video hardware. This slot has the digital video signals available which are generated by Denise. So there is no need to digitize the analog RGB signals at the video connector plus all the timing signals/clocks like HSYNC/VSYNC are available as well. The drawback compared to other solutions like the Indivison scandoubler is, that the board can be used on A2000 devices only.
For a 640x512 image at a color depth of 3x4 bit you need to store 320k x 12bit with a pixel clock of around 7 MHz. So I used two 256k x 16 bit high speed SRAMs as video storage (this turned out to be not overly smart, as I didn't have enough memory to store the horizontal/vertical retrace periods but needed lots of logic to prevent my scandoubler from capturing during these times). The SRAM needs to be a "SM624016" pin compatible device. I used a IS61WV25616BLL-10IL from ISSI, but many compatible devices are available. The RAM needs to be in a pin compatible 44 pin TSOP (Type II) package, need to run at 3,3V and requires a fast access time that can cope with the 28 MHz operating frequency (i.e. 35 ns).
In order to keep things cheap and simple (5V logic, no FPGA loading, ...) I decided to build the required glue logic into a CPLD instead of an FPGA (the second not overly smart move due to the limited logic resources).
The initial design was simple: Run the SRAM at four times the pixel clock. Write the current pixel from the Amiga to memory (two times) and read two pixels for the VGA output. So I needed to perform four RW cycles at 7 MHz pixel clock rate. So the SRAM needed to be operated at 4x7Mhz = 28 MHz. This clock was generated out of the 7 MHz Amiga (pixel) clock by a x4 clock multiplier device connected to the CPLD.
Unfortunately this design was too simple. In the era of CRT monitors, one was able to tweak the image with some trimmers on the back of the monitor, so that the 640x512 pixel image fitted to the screen. Today LCDs support only dedicated resolutions (like 640x480 or 800x600). As a result, I had to decide, if I want to have a 640x480 resolution fitting the screen but lacking the last 32 lines or a 800x600 resolution by adding some dead black lines to the bottom of the screen. I opted for the latter. Consequently I had to regenerate the entire timing for the VGA output and the refresh rate became slightly lower than 50/60 Hz (which seems to be OK for most screens).
Second challenge was to detect progressive and interlaced frames. In interlace mode, a 256 lines odd and even frame are sent at a rate of 50/60 Hz building a full picture at a rate of 25 Hz. Odd and even frames can be distinguished by the timing of the very first line. In progressive mode the same 256 lines frame is sent at a rate of 50/60 Hz (there are just odd frames). In order to provide a full 512 lines image for the VGA monitor, the data had to be placed on the odd and even lines consecutively.
As the Amiga supports 4096 colors (i.e. 4 bit per color) only, digital to analog conversion doesn't require fancy DA-converters but a cheap R2R ladder. The output can be connected to a high speed video opamp optionally.
Building the Flickerfixer
The flickerfixer comprises a Xilinx XC95144XL CPLD in a TQFP100 package (which requires some decent SMD soldering skills) plus a Pericom PI6C4511 by four clock multiplier to generate the required timing. An optional video opamp (mount resistor package R1, if you don't have a video opamp) and two 256k x 16 SRAMs as video storage and a 3,3V voltage regulator to drive the CPLD.
A Xilinx JTAG programmer cable is required to download the CPLD code to the CPLD using the 14 pin pinhead (standard Xilinx JTAG configuration).
Don't forget to set the jumper (located close to the clock device), to select the appropriate operation mode (the picture above).
Absolutely stunning, a crystal clear non blurry image ...
How to get it
The full package can be downloaded at Aminet.